SOC / IP
PHYSICAL DESIGN
PHYSICAL DESIGN
Physical design implementation is our forte. Our engineers are highly skilled in physical design implementation of various IPs like DDR, SERDES, USB, etc. Ambit spares no effort in hiring the best engineers with specialized skills and proven track record of IP hardening and who excel in chip level physical design end to end (RTL to GDS) implementations.
Synthesis:
- RTL code synthesis using DC/DCT/RC
- DFT insertion
- Low Power
- RTL-Gate Logical equivalence checks
PNR:
- Netlist to GDS delivery
- Partitioning and Floorplanning
- Clock tree synthesis; specialized in clock mesh, cloning, clock buffers, Muti-source CTS
- Routing; specialized in meeting tight arrival time skew requirements
- Power (UPF/CPF) aware PNR
- Flow automation and scripting
- Gate-Gate Logical equivalence checks
STA:
- Timing constraints development
- Timing closure
- Budgeting
- ECO iterations
- ETM generation and validation
- Enabling and validating special timing requirements
SIGNOFF:
- Logical equivalence checks
- EM, IR and other reliability requirements
- STA
- Physical verification- DRC/LVS