CURRENT OPPORTUNITIES

Sr. Engineer / MTS / SMTS

Qualification: B.Tech / M.Tech or equivalent from a reputed University

Experience: 2 - 8 years of relevant experience

Location: Bangalore / Hyderabad

Job Description
Responsible for all aspects of physical design and implementation. Responsibilities include chip floor plan, power / clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects.

High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;

Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical Designs

Should be independent, self-driven and a strong team player.

• Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii
• Must be familiar with Industry standard tools like ICC / Innovus / Encounter
• Should have expertise in Timing analysis and closure
• Should have Tcl and perl scripting skills
• Preferred experience in the latest technology nodes like 7nm/10nm
• Should be familiar with low-power design and their impact on Back end flow (power switches / Level shifter / Isolation cell / retention cells)

Sr. Engineer / MTS / SMTS

Qualification: B.Tech / M.Tech or equivalent from a reputed University

Experience: 2 - 8 years of relevant experience

Location: Bangalore / Hyderabad

Job Description
Strong in digital design fundamentals

Expertise in micro architecture development, design, RTL Coding & integration of IP blocks in ASIC/SoC designs

Very good understanding of timing requirements, synthesis flows and experience in formal verification flows

• Hands on experience of coding in Verilog and VHDL.
• Understanding of Power Intent, Power estimation and checks.
• Experience of Design rule checks and Clock domain crossing checks using Spyglass or similar tool.
• Specification writing.
• IP RTL development experience.
• Good knowledge of version control tools like Clearcase and Design sync.
• Strong in digital design fundamentals.
• Expertise in micro architecture development, design, RTL Coding & integration of IP blocks in ASIC / SoC designs.
• Very good understanding of timing requirements, synthesis flows and experience in formal verification flows.
• Design for test and Design for debug (DFx) is a plus.
• Very good understanding of system level architecture and validation flows.
• Highly motivated individuals and ability to deal with ambiguity.
• Ability to work in a team environment.
• Good hands-on expertise in Perl, Shell and Unix scripting.

Sr. Engineer / MTS / SMTS

Qualification: B.Tech / M.Tech or equivalent from a reputed University

Experience: 2 - 8 years of relevant experience

Location: Bangalore / Hyderabad

Job Description
Specify the DFT Architecture including JTAG functionality, boundary scan, Hierarchical scan, at-speed testing, I/O testing requirements, MBIST and Repair, Implement Test Logic.

Generate and debug test patterns Exposure to EDA tools viz. DC, LogicVision, Fastscan, Tetramax Good knowledge about all DFT concepts & ATPG Flow.

Vector Generation, ATPG Pattern Generation, Validation, Scan insertion and validation, Timing Analysis

Chip-level DFT insertion with sound knowledge of scan compression, MBIST & JTAG techniques

• Should have good post silicon DFT bringup and debug experience
• Hands on in multi-vendor DFT tools
• Create test plan for complex ASICs and drive the DFT implementation & verification
• Ability to guide people, multiplex many issues and set priorities
• Good communication and leadership skills

Sr. Engineer / MTS / SMTS

Qualification: B.Tech / M.Tech or equivalent from a reputed University

Experience: 2 - 8 years of relevant experience

Location: Bangalore / Hyderabad

Job Description

• Expert in UVM / OVM for Verification
• System verilog assertions • Perl • Functional + Code Coverage
• Verilog and VHDL
• Cadence IUS (preferred) or Mentor Questasim
• Image Sensor knowledge is a plus
• Experience with SPI / I2C is a plus